Effects of Parasitics and Interface Traps On Ballistic Nanowire FET In The Ultimate Quantum Capacitance Limit

Abstract

In this paper, we focus on the performance of a nanowire Field Effect Transistor (FET) in the Ultimate Quantum Capacitance Limit (UQCL) (where only one subband is occupied) in the presence of interface traps ($D_{it}$), parasitic capacitance ($C_L$) and source/drain series resistance ($R_{s,d}$) using a ballistic transport model and compare the performance with its Classical Capacitance Limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely, (i) gate voltage dependent capacitance, (ii) saturation of the drain current, (iii) the subthreshold slope and (iv) the scaling performance. To gain physical insights into these effects, we also develop a set of semi-analytical equations. The key observations are: (1) A strongly energy-quantized nanowire shows non-monotonic multiple peak C-V characteristics due to discrete contributions from individual subbands; (2) The ballistic drain current saturates better in the UQCL compared to CCL, both in presence and absence of $D_{it}$ and $R_{s,d}$; (3) The subthreshold slope does not suffer any relative degradation in the UQCL compared to CCL, even with $D_{it}$ and $R_{s,d}$; (4) UQCL scaling outperforms CCL in the ideal condition; (5) UQCL scaling is more immune to $R_{s,d}$, but presence of $D_{it}$ and $C_L$ significantly degrades scaling advantages in the UQCL.