Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation

Abstract

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.