Device Considerations for Nanophotonic CMOS Global Interconnects

Abstract

We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We derive the device requirements for sub 100 fJ/cm/bit interconnects including tuning power, serialization-deserialization energy, optical insertion losses, extinction ratio and bit error rates. Using CMOS with integrated nanophotonics as an example platform, we derive the energy/bit, linear and areal bandwidth density of optical interconnects. We also derive the targets for device performance which indicate the need for continued improvements in insertion losses (<8dB), laser efficiency, operational speeds (>40 Gb/s), tuning power (<100 {\mu}W/nm), serialization-deserialization (< 10 fJ/bit/Operation) and necessity for spectrally selective devices with wavelength multiplexing (> 6 channels).