Criticality Aware Multiprocessors

Abstract

Typically, a memory request from a processor may need to go through many intermediate interconnect routers, directory node, owner node, etc before it is finally serviced. Current multiprocessors do not give preference to any particular memory request. But certain memory requests are more critical to multiprocessor's performance than other requests. Example: memory requests from critical sections, load request feeding into multiple dependent instructions, etc. This knowledge can be used to improve the performance of current multiprocessors by letting the ordering point and the interconnect routers prioritize critical requests over non-critical ones. In this paper, we evaluate using SIMICS/GEMS infrastructure. For lock-intensive microbenchmarks, criticality-aware multiprocessors showed 5-15% performance improvement over baseline multiprocessor. Criticality aware multiprocessor provides a new direction for tapping performance in a shared memory multiprocessor and can provide substantial speedup in lock intensive benchmarks.