Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS2 FETs
Abstract
Clockwise to anti-clockwise hysteresis crossover in current-voltage transfer characteristics of field effect transistors (FETs) with graphene and MoS2 channels holds significant promise for non-volatile memory applications. However such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS2 FETs by using a gate-drain underlap design to induce a differential response from traps at the MoS2-HfO2 channel-gate dielectric interface to applied gate bias. The appearance of interface trap-driven anti-clockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS2 channel flake. The underlap design also enables room temperature tuning of the anti-clockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 and 65 ) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO2 traps to the clockwise and anti-clockwise hysteresis.