Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map

Abstract

In this paper, a novel chaotic map is introduced usinga voltage controlled negative differential resistance (NDR) circuitcomposed of ann-channel and ap-channel silicon-on-insulator(SOI) four-gate transistor (G4FET). The multiple gates of theG4FET are leveraged to create a discrete chaotic map with threebifurcation parameters. The three tunable parameters are thegain of a transimpedance amplifier (TIA), top-gate voltage ofn-channel G4FET, and top-gate voltage ofp-channel G4FET. Twomethods are proposed for building chaotic oscillators using thisdiscrete map. The effect of altering bifurcation parameters onchaotic operation is illustrated using bifurcation diagrams andLyapunov exponent. A design methodology for building flexibleand reconfigurable logic gate is outlined and the consequentenhancement in functionality space caused by the existence ofthree independent bifurcation parameters is demonstrated andcompared with previous work.