Hetero-structure Mode Space Method for Efficient Device Simulations

Abstract

The Hamiltonian size reduction method or the mode space method applicable to general heterogeneous structures is developed in this work. The effectiveness and accuracy of the method are demonstrated for four example devices of GaSb/InAs tunnel field effect transistor (FET), MoTe2/SnS2 bilayer vertical FET, InAs nanowire FET with a defect, and Si nanowire FET with rough surfaces. The Hamiltonian size is reduced to around 5 % of the original full Hamiltonian size without losing the accuracy of the calculated transmission and local density of states in a practical sense. The method developed in this work can be used with any type of Hamiltonian and can be applied to virtually any hetero-structure, so it has the potential to become an enabling technology for efficient simulations of hetero-structures.