Evaluation of $SU(3)$ smearing on FPGA accelerator cards

Abstract

Recent FPGA accelerator cards promise large acceleration factors for some specific computational tasks. In the context of Lattice QCD calculations, we investigate the possible gain of moving the $SU(3)$ gauge field smearing routine to such accelerators. We study Xilinx Alveo U280 cards and use the associated Vitis high-level synthesis framework. We discuss the possible pros and cons of such a solution based on the gathered benchmarks.