Design and implementation of an out-of-order execution engine of floating-point arithmetic operations

Abstract

In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out-of-order execution engine of floating-point arithmetic operations for the Lagarto II core. A first proposal covers the design of a low power consumption issue queue for out-of-order processors, register bank, bypass network, and the functional units for addition/subtraction, multiplication, division/reciprocal, and Fused Multiply Accumulate (FMAC) confirming with the IEEE-754 standard. The design supports double-precision format and denormalized numbers; A second proposal is based on a pair of FMAC as functional units which can perform almost all Floating-point operations, this design is more beneficial in area, performance, and energy efficiency compared with the first version.