Towards sub-30nm Contacted Gate Pitch, Forked Contact and Dynamically-Doped Nanosheets to Enhance Si and 2D Materials Device Scaling

Abstract

We propose a novel Forked-Contacts, Dynamically-Doped Multigate transistor as ultimate scaling booster for both Si and 2D materials in aggressively-scaled nanosheet devices. Using accurate dissipative DFT-NEGF atomistic-simulation fundamentals and cell layout extrinsics, we demonstrate superior and optimal device characteristics and invertor energy - delays down to sub-30-nm pitches, i.e., a 10 nm scaling boost compared to the nanosheet MOSFET references.