Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays -- Part I: Robustness-driven Device-Circuit Co-Design and System Implications

Abstract

In-memory computing (IMC) utilizing synaptic crossbar arrays is promising for energy-efficient deep neural network (DNN) accelerators. Various technologies (CMOS and post-CMOS) have been explored as synaptic device candidates, each with its own pros and cons. In this work, we perform a design space exploration and comparative evaluation of four technologies viz. 8T SRAMs, ferroelectric transistors (FeFETs), resistive RAMs (ReRAMs) and spin-orbit torque magnetic RAMs (SOT-MRAMs) in the context of IMC robustness and DNN accuracy. For a fair comparison, we carefully optimize each technology specifically for synaptic crossbar design accounting for device and circuit non-idealities. By integrating different technologies into a cross-layer simulation flow based on physical models of synaptic devices and interconnects, we present insights into various device-circuit interactions. Based on the optimized designs, we obtain inference results for ResNet-20 on CIFAR-10 dataset. Among the four technologies, we show that FeFETs-based DNNs achieve the highest accuracy (followed closely by ReRAMs) and the largest resilience to process variations due to the compactness and high ON/OFF current ratio of FeFET bit-cells. In Part II of this paper, we expand the technology evaluation considering various device-circuit design knobs used for crossbar arrays.