A Joint Optimization of Buffer and Splitter Insertion for Phase-Skipping Adiabatic Quantum-Flux-Parametron Circuits

Abstract

Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device technology with six orders of magnitude lower power than CMOS. However, AQFP is challenged by the fact that every gate must be clocked, where proper data transfer requires connected gates to have shifted but overlapping clocks. As a result, buffers need to be used to balance re-convergent logic paths, a problem that is exacerbated by every multi-node fanout needing a tree of clocked splitters. Recent AQFP circuit design techniques have offered an opportunity to reduce buffer costs by supporting a notion of phase-skipping but the EDA support for these advanced circuits is limited. This paper proposes the first algorithm to optimize buffer and splitter insertion for phase-skipping AQFP circuits and achieves over 31\% savings over existing buffer reduction schemes and up to 74\% savings in buffers and splitter costs over the SOTA non-phase skipping circuits.