Practical quantum advantage on partially fault-tolerant quantum computer

Abstract

Achieving quantum speedups in practical tasks remains challenging for current noisy intermediate-scale quantum (NISQ) devices. These devices always encounter significant obstacles such as inevitable physical errors and the limited scalability of current near-term algorithms. Meanwhile, assuming a typical architecture for fault-tolerant quantum computing (FTQC), realistic applications inevitably require a vast number of qubits, typically exceeding $10^6$, which seems far beyond near-term realization. In this work, to bridge the gap between the NISQ and FTQC eras, we propose an alternative approach to achieve practical quantum advantages on early-FTQC devices. Our framework is based on partially fault-tolerant logical operations to minimize spatial overhead and avoids the costly distillation techniques typically required for executing non-Clifford gates. To this end, we develop a space-time efficient state preparation protocol to generate an ancillary non-Clifford state consumed for implementing an analog rotation gate with an arbitrary small angle $\theta$ and a remarkably low worst-case error rate below $\mathcal{O}(|\theta| p_{\text{ph}})$, where $p_{\text{ph}}$ is the physical error rate. Furthermore, we propose several error suppression schemes tailored to our preparation protocol, which are essential to minimize the overhead for mitigating errors. Based on this framework, we present several promising applications that leverage the potential of our framework, including the Trotter simulation and quantum phase estimation (QPE). Notably, we demonstrate that our framework allows us to perform the QPE for $(8\times 8)$-site Hubbard model with fewer than $4.9\times 10^4$ qubits and an execution time of 9 days (or 12 minutes with full parallelization) under $p_{\text{ph}}=10^{-4}$, which is significantly faster than recent classical estimation with tensor network techniques (DMRG and PEPS).