3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography

Abstract

To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes down to the few-nm regime, which require atomic-scale metrology to identify and resolve performance-limiting fabrication challenges. X-ray methods deliver three-dimensional imaging of integrated circuits but lack the spatial resolution to characterize atomic-scale features, while conventional electron microscopy offers atomic-scale imaging but limited depth information. We demonstrate how multislice electron ptychography (MEP), a computational electron microscopy technique with sub-\r{A}ngstr\"om lateral and nanometer-scale depth resolution, enables 3D imaging of buried features in devices. By performing MEP on prototype gate-all-around transistors we uncover and quantify distortions and defects at the interface of the 3D gate oxide wrapped around the channel. We find that the silicon in the 5-nm-thick channel gradually relaxes away from the interfaces, leaving only 60% of the atoms in a bulk-like structure. Quantifying the interface roughness, which was not previously possible for such small 3D structures but strongly impacts carrier mobility, we find that the top and bottom interfaces show different atomic-scale roughness profiles, reflecting their different processing conditions. By measuring 3D interface roughness simultaneously with strain relaxation and atomic-scale defects, from a single MEP dataset, we provide direct experimental values of these performance-limiting parameters needed for modeling and early fabrication optimization.