Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure

Abstract

The performance and scalability of two-dimensional (2D) field-effect transistors (FETs) are strongly influenced by geometry-defined electrostatics. In most 2D FET studies, the gate overlaps with the source and drain electrodes, allowing the gate potential to modulate the 2D semiconductor underneath the electrodes and ultimately effect carrier transport at the metal-semiconductor interface - a phenomenon known as contact gating. Here, a symmetric dual-gate structure with independently addressable back and top gates is employed to elucidate the impact of contact gating on a monolayer MoS2 channel. Unlike previous studies of contact gating, this symmetric structure enables quantification of the phenomena through a contact gating factor, revealing a 2x enhancement in on-state performance in long-channel devices. At scaled dimensions (50 nm channel and 30 nm contact length), the influence of contact gating becomes amplified, yielding a 5x increase in on-state performance and a 70% reduction in transfer length when contact gating is present. Since many reported record-performance 2D FETs employ back-gate geometries that inherently include contact gating, these results establish contact gating as a critical and previously underappreciated determinant of device performance in the 2D FET landscape.