Depth optimization of CNOT ladder circuits

Abstract

The increasing depth of quantum circuits presents a major limitation for the execution of quantum algorithms, as the limited coherence time of physical qubits leads to noise that manifests as errors during computation. In this work, we focus on CNOT ladder circuits, which find applications in several quantum computing tasks, including the preparation of GHZ states, the implementation of fan-out and long-range CNOT gates, fermionic simulations, and the construction of ansatz circuits for variational quantum computing. The linearly increasing depth of a CNOT ladder circuit can be exchanged for constant CNOT depth at the expense of wider circuits that rely on mid-circuit measurements and classically controlled operations. Our error analysis shows that the choice between these two constructions depends on the relative difference between CNOT and idling error rates. Overall, the technique developed in this work enables low-depth implementations of circuits that are ubiquitous in quantum computing algorithms.