Graphene FET Process and Analysis Optimization in 200 mm Pilot Line Environment

Abstract

The maturity of the chemical vapor deposition graphene-based device processing has increased from chip level demonstrations to wafer-scale fabrication in the past few years. Due to this wafer-scale, electrical characterization and analysis of the fabricated devices has become increasingly important to enable extraction of multiple parameters with minimal number of measurements for the quality control purposes critical for industrial uptake of 2D materials-based devices. As a crucial step, we demonstrate optimization of complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL) compatible graphene field-effect transistor (GFET) fabrication and analysis including the gate stack, bottom contact, graphene patterning and encapsulation process steps. The analysis methods include atomic force microscopy, scanning electron microscopy and most importantly electrical characterization. The electrical characterization focuses on comparing different test structures and extraction methods for mobility, contact resistance, IV-curve hysteresis and doping parameters. The comparison shows that the selected measurement test structures and analysis methods can have a large impact on the extracted values and should thus be considered when comparing data sets between different sources. The analysis shows that the optimized process offers high device yield of 98 % with good doping uniformity, contact resistance and mobility as well as low IV-curve hysteresis values on 200 mm wafers.