In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs

Abstract

Timing degradation in SRAM-based FPGAs arises from multiple physical mechanisms that manifest differently in the routing fabric, most notably power-distribution-network (PDN) marginality and configuration-induced routing perturbations. Existing in-situ timing monitors provide limited insight into the physical origin, spatial structure, or statistical characteristics of the degradation. This paper presents a scalable in-situ timing diagnosis architecture that enables fine-grained, routing-aware characterization of timing behavior directly within the FPGA fabric during normal operation. The proposed approach combines non-intrusive delay taps placed at routing switch-matrix boundaries with distributed phase-swept delay monitoring elements and centralized statistical analysis. By extracting probabilistic delay distributions rather than binary timing margins, the framework captures both mean delay shifts and timing variability across spatially distributed routing locations. Experimental results obtained on a modern SRAM-based FPGA show that PDN-induced timing degradation produces globally correlated delay shifts with minimal change in variance, whereas routing-induced perturbations exhibit localized, topology-dependent delay growth and increased timing dispersion. Spatial correlation analysis and two-dimensional correlation heatmaps further reveal distinct signatures that enable systematic differentiation between these mechanisms. The presented architecture operates concurrently with an active user design and does not require external instrumentation, radiation sources, or design modification. These results establish a practical foundation for in-situ timing diagnosis, reliability assessment, and architecture-aware timing management in large FPGA-based systems.