ORRAM: An OpenROAD-Integrated RAM Generator Using Standard Cells

Abstract

Memory inference remains a significant challenge in turnkey ASIC design flows. Inferring flip-flops from RTL can create thousands of densely interconnected instances which dramatically slow down design flows and impede performance. Memory compilers address this issue, although they are third-party tools which are often PDK-specific and may require specialized cells not in the base PDK. To address these shortcomings, we present ORRAM, a standard-cell-based memory generator built as a native module within OpenROAD. Given a standard cell library, ORRAM produces a fully placed and routed RAM block requiring no custom bitcells or external tooling, with timing verification via OpenSTA rather than SPICE simulation. ORRAM supports arbitrary word sizes, word counts, mask granularities, multi-port read configurations, column muxing, latch-based storage, and automatic PDK-agnostic cell selection, making it compatible with most standard cell libraries including sky130hd and NanGate45. Evaluated on SkyWater 130nm, ORRAM matches the bit density of historical DFFRAM results while offering a significantly expanded feature set. The source code is available as part of the OpenROAD project.