Gate capacitance of back-gated nanowire field-effect transistors
Abstract
Gate capacitances of back-gated nanowire field-effect transistors (NW-FETs) are calculated by means of finite element methods and the results are compared with analytical results of the ``metallic cylinder on an infinite metal plate model''. Completely embedded and non-embedded NW-FETs are considered. It is shown that the use of the analytical expressions also for non-embedded NW-FETs gives carrier mobilities that are nearly two times too small. Furthermore, the electric field amplification of non-embedded NW-FETs and the influence of the cross-section shape of the nanowires are discussed.
Turn this paper into a full lesson
ArcXiv compiles a staged curriculum from this paper: 8-12 lessons across beginner → advanced, synthesised section guides, visuals, flashcards, a quiz, exercises, and on-demand deep dives per section. Grounded in the abstract, never invented.