Lapis SOI Pixel Process

Abstract

0.2 um fully-depleted SOI technology has been developed a for X-ray pixel detectors. To improve the detector performance, some advanced process technologies are developing continuously. To utilize the high resistivity FZ-SOI, slow ramp up and ramp down recipes are applied for the thermal processes in both of SOI wafer fabrication and pixel detector process. The suitable backside treatment is also applied to prevent increase of leakage current at backside damaged layer in the case of full depletion of substrate. Large detector chip about 66mm width and 30mm height can be obtained by stitching exposure technique for large detector chip. To improve cross-talk and radiation tolerance, the nested well structure and double- SOI wafer are now under investigation for advanced pixel structure.