Fast C-V method to mitigate effects of deep levels in CIGS doping profiles

Abstract

In this work, methods to determine more accurate doping profiles in semiconductors is explored where trap-induced artifacts such as hysteresis and doping artifacts are observed. Specifically in CIGS, it is shown that this fast capacitance-voltage (C-V) approach presented here allows for accurate doping profile measurement even at room temperature, which is typically not possible due to the large ratio of trap concentration to doping. Using deep level transient spectroscopy (DLTS) measurement, the deep trap responsible for the abnormal C-V measurement above 200 K is identified. Importantly, this fast C-V can be used for fast evaluation on the production line to monitor the true doping concentration, and even estimate the trap concentration. Additionally, the influence of high conductance on the apparent doping profile at different temperature is investigated.