Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS

Abstract

Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are reconstructed by reading out voltages from a 16-element electrode array and processing the data off-chip, and sources of variation in reconstruction are discussed. The EIT system presented in this work serves as a proof-of-concept towards using CMOS as a platform for co-integrated microfluidics and electronics.