Testing and Characterization of Wafer-Scale MAPS Prototypes for the ALICE ITS3 Upgrade

Abstract

The ALICE experiment will upgrade the innermost three layers of its vertexing detector, the Inner Tracking System (ITS), during the next LHC Long Shutdown (LS3) with a novel, bent, ultra-light MAPS-based tracker. Six wafer-scale sensor chips will be bent into three cylinders, held in place only by carbon foam, leaving no material except for the silicon die in most of the ALICE central barrel acceptance. Two prototype ASICs, approximately $25.9\,\mathrm{cm}$ in length, called MOSS (MOnolithic Stitched Sensor) and MOST (MOnolithic Stitched sensor with Timing), have been produced. These two chips follow complementary approaches to evaluate the use of stitched CMOS sensors for the first time in an HEP experiment. This article gives an overview of powering tests, functional studies, pixel matrix characterization, and in-beam tests of both test structures. The overall yield of MOSS is measured to be approximately $76\,\%$ per region (1/80th of a chip). This number takes into account powering, as well as functional aspects such as digital and analog pulsing. Two major failure modes have been identified and understood: short in the power grid of the chip and readout issues, that can be clearly attributed to the readout architecture design. Disregarding these issues, the overall yield increases to about $98\,\%$ per region. Furthermore, it is shown that MOSS can operate with $>99\,\%$ efficiency and $<10^{-1}\,\mathrm{hits/pixel/s}$ fake-hit rate up to $4\,\mathrm{kGy}$ TID and $4\times 10^{12}\,\mathrm{1~MeV~n_{eq}~cm^{-2}}$ NIEL. The MOST prototype successfully demonstrated use of power gating, which allows for disconnected parts of the pixel matrix from the power grid in case of shorts. MOSS and MOST successfully proved that designing stitched wafer-scale sensors is feasible and deliver valuable input for the design of the final ITS3 ASIC.