VERITAS 2.3.1: Optimisation and Characterisation of the Enhanced Readout ASIC for the NewAthena Wide Field Imager

Abstract

VERITAS 2.3.1 is the next iteration of the VErsatile Readout based on Integrated Trapezoidal Analogue Shapers (VERITAS) integrated circuit (IC) architecture for high-speed, low-noise readout of DEPleted Field Effect Transistor (DEPFET) detectors in the Wide Field Imager (WFI) on ESA's NewAthena X-ray satellite. Building on VERITAS 2.3, which demonstrated a short processing time of 2.5 us per readout and a system noise target of about 3 e- ENC RMS, the VERITAS 2.3.1 revision has been improved with additional features and targeted optimisations of existing analogue and digital blocks, alongside refined layout routing to reduce parasitic effects, to improve transient behavior, cross talk, manufacturability, and reliability while preserving the proven VERITAS architecture. The functionality and performance of VERITAS 2.3.1 was characterised in two steps. First by using a dedicated application specific integrated circuit (ASIC) only test setup. Second, a full scale module test setup is used, with integrated DEPFET sensors and readout electronics, under vacuum and at mission like temperatures. This paper presents the design updates and implementation details of the VERITAS 2.3.1, compares its measured performance to that of VERITAS 2.3, and discusses the impact of the added features, block-level optimisations, and routing improvements on overall system performance.