DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference
Yousef Sadegheih, Dorit Merhof, Muhammad Usman
Abstract
U-Net inference for brain-tumor segmentation requires billions of multiply-accumulate operations, motivating hardware that can reduce computation dynamically rather than relying only on fixed precision or static model compression. Most-significant-digit-first (MSDF) arithmetic exposes the leading digits of a result during computation, enabling output-dependent decisions before the full value is generated. This paper presents an MSDF accelerator for quantized U-Net segmentation with a two-stage grouped processing element supporting signed INT8 operands and in-stream bias accumulation. Four runtime mechanisms operate directly on the output digit stream: exact early negative detection (END) in ReLU layers, exact sign-only decision making in the segmentation head, calibrated low-order-digit skipping, and calibrated pruning. The two approximate mechanisms are selected offline under an accuracy constraint, while execution requires only lightweight control and does not modify the stored weights. On a residual U-Net trained with nnU-Net for BraTS, the proposed mechanisms reduce digit cycles by 38.38\% while achieving a mean Dice score of 80.58\% on 73 held-out cases, compared with 81.20\% for the floating-point model; the exact mechanisms alone reduce cycles by 18.79\% without altering the quantized output. Synthesized in 45~nm, the processing element operates at 500~MHz, occupies 0.858~mm2, and consumes 0.726~mJ per 192×192 patch under switching-activity-annotated power analysis. A projected eight-output accelerator with shared activation delivery achieves 16.6~ms latency and 1.67~mJ per patch.
Create a lesson
Related papers
A Hybrid and Hierarchical Ray Tracing Method for Efficient 3D Gaussian Rendering
Tiancheng Zhao, Sixu Li, Yuzhou Chen et al.
Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
Seungki Hong, Kyeongwon Jeong, Taekwang Jang
Hardware-in-the-Loop Demo of a Cooperative Intersection where Cars don't Stop
Lorenzo Farina, Matteo Piccoli, Salvatore Iandolo et al.
TPCS: A Cycle-Level Simulation Paradigm with Native Execution Semantics for RTL Modeling and Generation
Chengzhen Meng, Xiaoyu Li, Chen Bai et al.
CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support
Jingqun Zhang, Maohua Nie, Jiayi Wang et al.
VortexSynth: Profile-guided benchmark reconstruction for GPU architecture research
Huanzhi Pu, Chulhyung Park, Chihyo Ahn et al.