Control-Noise Trade-offs in Industrially Integrated ${}^{28}\mathrm{Si}/\mathrm{SiGe}$ Spin-1/2 Qubits

Abstract

Scaling silicon spin qubits to fault-tolerant processors requires semiconductor foundry integration, yet it remains unclear how industrial fabrication and dense device integration affect qubit control and noise. Here we study ${}^{28}\mathrm{Si}/\mathrm{SiGe}$ electron spin-1/2 qubits fabricated using Intel's industry-compatible 300 mm process and incorporating micromagnets for electrically driven spin resonance, using a high-performance device fabricated in the RIKEN research cleanroom as a reference. Primitive $π/2$-gate fidelities reach the 99.99% level in the Intel devices, which also exhibit longer idle coherence, weaker low-frequency correlations and reduced qubit-to-qubit variability across several measured characteristics. In the present Intel devices, the micromagnets are integrated inline with the back-end-of-line (BEOL) contact routing, with their separation from the quantum well set through the vertical stack design. Relative to the reference, their larger separation contributes to weaker longitudinal and transverse magnetic-field gradients. The weaker longitudinal gradient suppresses the conversion of charge noise into qubit-frequency fluctuations, whereas the weaker transverse gradient reduces electrically driven spin-resonance efficiency and makes drive-dependent errors relevant at lower Rabi frequencies. Additional BEOL routing and metal levels required for two-dimensional arrays make such placement decisions increasingly consequential when scaling. These results establish an integration-level control-noise trade-off linking micromagnet placement within densely routed layouts to achievable gate performance, while very high-fidelity operation remains possible in industrially fabricated devices.