Modelling background charge rearrangements near single-electron transistors as a Poisson process

Abstract

Background charge rearrangements in metallic single-electron transistors are modelled in two-level tunnelling systems as a Poisson process with a scale parameter as only variable. The model explains the recent observation of asymmetric Coulomb blockade peak spacing distributions in metallic single-electron transistors. From the scale parameter we estimate the average size of the tunnelling systems, their density of states, and the height of their energy barrier. We conclude that the observed background charge rearrangements predominantly take place in the substrate of the single-electron transistor.