Defragmenting the Module Layout of a Partially Reconfigurable Device
Jan van der Veen, Sandor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Juergen Teich
Abstract
Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by propose an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a two-dimensional strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve two-dimensional defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances.
Create a lesson
Related papers
Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS
David Rostcheck
Energy Efficient Near-Threshold Voltage Massive MIMO Computing
MD Salman Sakib, Mehdi Safarpour, Pejman Ghasemzadeh et al.
Data Center Agglomeration and Power Infrastructure Capacity in the United States
Yutong Ma
Hardwired Distributed Processing Units for Inference: Neural Decisions at the Sensor that Free the Host
Raj Mali
Phantom: Temporal Caching for Diffusion Models
Yuzhe Fu, Cong Guo, Zishan Shao et al.
Scheduling Data to Compute: Hierarchical Data Pipelining for LLM Training on AMD GPUs
Gengyu Rao, Ghadeer Ahmed H Alabandi, Su Ann Chong et al.