Evaluation of Power-Clock Waveforms for Positive Feedback Adiabatic Logic in 16 nm FinFET Technology

Abstract

Adiabatic logic can recover part of the energy stored on load capacitances through quasi-reversible switching, but its waveform-optimized operation in FinFET technology and at multi-GHz frequencies remains underexplored. This work investigates Positive Feedback Adiabatic Logic (PFAL) in the TSMC 16 nm FinFET process. A functionally complete PFAL gate library is designed, verified, and characterised using energy-delay product optimization over power-clock amplitude, frequency, and waveform shape. The power-clock sweep shows that the minimum-energy waveform approaches a triangular shape rather than a conventional trapezoid. The optimized single-gate PFAL cells achieve up to 3.83x lower energy than equivalent static CMOS gates, while sinusoidal excitation improves energy by up to 1.32x compared with trapezoidal excitation and extends the valid operating range. The library is then used to construct larger combinational circuits, including a 2:1 multiplexer, a 4-bit ripple carry adder, and a 4-bit Brent-Kung carry look-ahead adder. The carry look-ahead adder reaches a gain of up to 5.3x compared with the static CMOS energy estimate for the triangular power-clock.