Readout chain of SPD DAQ system

Abstract

The Spin Physics Detector (SPD) experiment at the NICA collider of the Joint Institute for Nuclear Research (JINR) aims to study the spin structure of the nucleon and spin-related phenomena. The experimental conditions, including the high interaction rate and the large number of readout channels, require a triggerless data acquisition system with high throughput and a scalable architecture. This work presents a hardware implementation of the readout chain that extends the previously proposed SPD DAQ architecture. The chain is based on two levels of concentrators. The L1 concentrator provides the interface between the front-end electronics and the next system level and distributes synchronous signals. The L2 concentrator aggregates data streams from several L1 concentrators before transmitting them to the computing system. A key feature of the L2 implementation is the offloading of data reception, buffering, and aggregation from the host CPU to the FPGA, motivated by the large number of small packets generated by the readout electronics. The developed hardware platforms and their operating logic are presented, together with experimental results for the main interfaces and data-path components. The obtained results demonstrate the feasibility of the proposed hardware architecture and its application in a scalable SPD data acquisition system.