Accelerating LLM Decoding with In-DRAM Parallelism
Kevin Xu, Tatsuya Kubo, Daichi Tokuda, Shinya Takamaeda-Yamazaki, Issei Sato
Abstract
Autoregressive decoding of large language models (LLMs) on edge devices is dominated by memory-bound general matrix--vector multiplication (GeMV) operations. Processing-using-DRAM (PUD) is a promising computing paradigm that can alleviate this bottleneck by reducing processor--memory data transfers and enabling massively parallel computation within DRAM (e.g., across 65,536 columns). However, weight matrices in individual LLM layers (e.g., a QKV matrix in Llama3 8B with 6,144 rows) are typically too small to fully utilize parallelism in PUD. To address this challenge, we propose an algorithm--system co-design for PUD-based LLM inference. At the algorithm level, we enable a subsequent projection to be packed with the current projection by reformulating it as a computation on the current residual state plus a correction for the residual update. Layer redundancy allows this correction to be approximated using fewer bit-serial steps. At the system level, we tailor data mapping and execution to improve utilization of either columns within DRAM subarrays (SIMD) or independently controlled banks (MIMD). Overall, we achieves up to 1.41× end-to-end decoding speedup over the PUD baseline, corresponding to a 2.45× speedup over processor-based execution.
Create a lesson
Related papers
HyPAIC: Personal AI Computer with High Bandwidth Flash for High Performance Trillion-Parameter LLM Inference
Minho Ha, Myunghyun Rhee, Euiseok Kim et al.
A Cross-Domain Matrix Engine for Signal Processing and Deep Neural Net Inference
Mehdi Safarpour
In-depth data movement characterization of DNA read mapping algorithms
Berkan Şahin, Ecem İlgün, Klea Zambaku et al.
TinyML Hits the Memory Wall: A Benchmark of Ten Sub-Watt Edge Devices
Pietro Bonazzi, Luigi Capogrosso, Ahmet Celik et al.
PagedMoE: Cross-Precision Expert Caching for Token-Level Dynamic Precision in SSD-Resident MoE Inference
Yutong Lin, Yingdi Shan, Shaoyuan Chen et al.
Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor
Yihang Dai, Shuyu Xu, Yinfeng Zhou et al.