October 2007 arXiv papers — page 13

T. Simunic

Fast wireless access has rapidly become commonplace. Wireless access points and Hotspot servers are sprouting everywhere. Battery lifetime continues to be a critical issue in mobile computing. This paper first gives an overview of WLAN energy saving strategies, followed by an illustration of a system-level methodology for saving power in heterogeneous wirele

Raul Blazquez, Fred Lee, David Wentzloff, Brian Ginsburg

Ultra-wideband (UWB) communication is an emerging wireless technology that promises high data rates over short distances and precise locationing. The large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges. This paper addresses these challenges using two UWB transceivers and a discrete prototy

Andrew Duller, Daniel Towner, Gajinder Panesar, Alan Gray

This paper briefly describes the picoArray? architecture, and in particular the deterministic internal communication fabric. The methods that have been developed for debugging and verifying systems using devices from the picoArray family are explained. In order to maximize the computational ability of these devices, hardware debugging support has been kept t

I. Papaefstathiou, T. Orphanoudakis, G. Kornaros, C. Kachris

One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the performanc

Sandro V. Silva, Sergio Bampi

The JPEG2000 standard defines the discrete wavelet transform (DWT) as a linear space-to-frequency transform of the image domain in an irreversible compression. This irreversible discrete wavelet transform is implemented by FIR filter using 9/7 Daubechies coefficients or a lifting scheme of factorizated coefficients from 9/7 Daubechies coefficients. This work

Massimo Conti, Daniele Moretti

The SystemC modules of the Link Manager Layer and Baseband Layer have been designed in this work at behavioral level to analyze the performances of the Bluetooth standard. In particular the probability of the creation of a piconet in presence of noise in the channel and the power reduction using the sniff and hold mode have been investigated.

Zoya Dyka, Peter Langendoerfer

Securing communication channels is especially needed in wireless environments. But applying cipher mechanisms in software is limited by the calculation and energy resources of the mobile devices. If hardware is applied to realize cryptographic operations cost becomes an issue. In this paper we describe an approach which tackles all these three points. We imp

Andres Takach, Bryan Bowyer, Thomas Bollaert

The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require developing the micro architecture, coding the RTL, and verifying the generated RTL against the original functional C or MATLAB specification. This paper describes a C-based design flow t

Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin

Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows 353 times faster than pin-accurate RTL model while main

G. Chen, M. Kandemir, M. Karakoy

While loop restructuring based code optimization for array intensive applications has been successful in the past, it has several problems such as the requirement of checking dependences (legality issues) and transformation of all of the array references within the loop body indiscriminately (while some of the references can benefit from the transformation,

Kris Tiri, Ingrid Verbauwhede

This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive sim

Hannu Heusala, Jussi Liedes

The idea of design domain specific Mother Model of IP block family as a base of modeling of system integration is presented here. A common reconfigurable Mother Model for ten different standardized digital OFDM transmitters has been developed. By means of a set of parameters, the mother model can be reconfigured to any of the ten selected standards. So far t

R. Elbaz, L. Torres, G. Sassatelli, P. Guillemin

The widening spectrum of applications and services provided by portable and embedded devices bring a new dimension of concerns in security. Most of those embedded systems (pay-TV, PDAs, mobile phones, etc...) make use of external memory. As a result, the main problem is that data and instructions are constantly exchanged between memory (RAM) and CPU in clear

M. Scholive, V. Beroulle, C. Robach, M. L. Flottes

Our goal is to produce validation data that can be used as an efficient (pre) test set for structural stuck-at faults. In this paper, we detail an original test-oriented mutation sampling technique used for generating such data and we present a first evaluation on these validation data with regard to a structural test.

R. Ruiz-Sautua, M. C. Molina, J. M. Mendias, R. Hermida

Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, its effectivene

Hala A. Farouk, Magdy Saeb

The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. In this exertion, an improved micro-architecture Field Programmable Gate Array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed

O. Ozturk, H. Saputra, M. Kandemir, I. Kolcu

As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements, power, real-time predictability, and reliability. In particular, many modern embedded systems operate under tight memory space constraints. One way of satisfying these

Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid

The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor blocks. The particular behavioral specification we consider is an intuitive user-created network diagram of sensor blocks, each block having a pre-defined combinational or sequentia

Paul Rosinger, Bashir Al-Hashimi, Krishnendu Chakrabarty

Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due

Javier Resano, Daniel Mozos, Francky Catthoor

Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Reconfigurable Hardware (DRHW) is a promising candidate to provide this flexibility but, currently, not sufficient run-time scheduling support to deal with the run-time reconfigurations exists. Mo

Alexandre M. Amory, Marcelo Lubaszewski, Fernando G. Moraes, Edson I. Moreno

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test so

Robert Bai, Nam-Sung Kim, Tae Ho Kgil, Dennis Sylvester

In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expanded as a result of cache misses. Ou

He Hai, Zhong Yi-Fang, Cai Chi-Lan

Complex real-time control system is a software dense and algorithms dense system, which needs modern software engineering techniques to design. UML is an object-oriented industrial standard modeling language, used more and more in real-time domain. This paper first analyses the advantages and problems of using UML for real-time control systems design. Then,

Florent Hivert, Jean-Christophe Novelli, Jean-Yves Thibon

Let M_n be the n! * n! matrix indexed by permutations of S_n, defined by M_n(sigma,tau)=1 if every descent of tau^{-1} is also a descent of sigma, and M_n(sigma,tau)=0 otherwise. We prove the following result, conjectured by P. Dehornoy: the characteristic polynomial P_n(x)=|xI-M_n| of M_n divides P_{n+1}(x) in Z[x].

Konstantin Pankrashkin

We consider perturbations of Hamiltonians whose Fourier symbol attains its minimum along a hypersurface. Such operators arise in several domains, like spintronics, theory of supercondictivity, or theory of superfluidity. Variational estimates for the number of eigenvalues below the essential spectrum in terms of the perturbation potential are provided. In pa

Volker J. Schmid, Brandon Whitcher, Anwar R. Padhani, N. Jane Taylor

Imaging in clinical oncology trials provides a wealth of information that contributes to the drug development process, especially in early phase studies. This paper focuses on kinetic modeling in DCE-MRI, inspired by mixed-effects models that are frequently used in the analysis of clinical trials. Instead of summarizing each scanning session as a single kine

Massimiliano Chiorboli

Final states with leptons, jets and missing transverse energy are a promising way to detect Supersymmetry at the Large Hadron Collider. Results of simulation studies performed by the CMS and ATLAS collaborations are presented. The discovery of new physics is shown to be possible within the first fb^-1 of collected integrated luminosity.

R. F. Jameson, S. L. Casewell, N. P. Bannister, N. Lodieu

The proper motion measurements for 143 previously known L and T dwarfs are presented. From this sample we identify and discuss 8 high velocity L dwarfs. We also find 4 new wide common proper motion binaries/multiple systems. Using the moving cluster methods we have also identified a number of L dwarfs that may be members of the Ursa Major (age ~400 Myr), the

Lukasz Cwiklik

Kinetics of model catalytic processes proceeding on inhomogeneous surfaces is studied. We employ an extended mean-field model that takes into account surface inhomogeneities. The influence of surface diffusion of adsorbent on the kinetics of the catalytic process is investigated. It is shown that diffusion is responsible for differences in the reaction rate

M. Circella

In this paper, we illustrate the main features of the electronics and data acquisition systems of the ANTARES apparatus, a large volume, deep-sea neutrino telescope under construction in the Mediterranean Sea off the coast of Toulon, France. The apparatus consists of an array of 900 large-area photomultipliers arranged on 12 detection lines, 5 of which are i

J. M. Almendros-Jiménez, A. Becerra-Terón, F. J. Enciso-Baños

Extensible Markup Language (XML) is a simple, very flexible text format derived from SGML. Originally designed to meet the challenges of large-scale electronic publishing, XML is also playing an increasingly important role in the exchange of a wide variety of data on the Web and elsewhere. XPath language is the result of an effort to provide address parts of

J. Bruedern, T. D. Wooley

By means of the Hardy-Littlewood method, we apply a new mean value theorem for exponential sums to confirm the truth, over the rational numbers, of the Hasse principle for pairs of diagonal cubic forms in thirteen or more variables.

R. Ranjith, B. Kundys, W. Prellier

Artificial superlattices of (BiFeO3)m(SrTiO3)m (m= 1 to 10 unit cells) consisting of multiferroic BiFeO3 and insulating SrTiO3 layers were fabricated on (100)-oriented SrTiO3 substrates by pulsed laser ablation. The remnant polarization and leakage current behavior were studied varying the periodicity (8-80A) of the superlattice. The leakage current was redu

Sven Wedemeyer-Böhm, Friedrich Wöger

The chromosphere of the quiet Sun is a highly intermittent and dynamic phenomenon. Three-dimensional radiation (magneto-)hydrodynamic simulations exhibit a mesh-like pattern of hot shock fronts and cool expanding post-shock regions in the sub-canopy part of the inter-network. This domain might be called "fluctosphere". The pattern is produced by prop

Leonardo Camara, Bruno Scardua

We determine topological and algebraic conditions for a germ of holomorphic foliation $\mathcal F(X)$ induced by a generic vector field $X$ on $(\mathbb{C}^{3},0)$ to have a holomorphic first integral, i.e., a germ of holomorphic map $F \colon(\mathbb{C}^{3},0)\longrightarrow(\mathbb{C}^{2},0)$ such that the leaves of $\mathcal F(X)$ are contained in the lev

G. Jackeli

I review the microscopic spin-orbital Hamiltonian and ground state properties of spin one-half spinel oxides with threefold $t_{2g}$ orbital degeneracy. It is shown that for any orbital configuration a ground state of corresponding spin only Hamiltonian is infinitely degenerate in the classical limit. The extensive classical degeneracy is lifted by the quant

Guy Cohen, Oded Hod, Eran Rabani

The study of nanospintronic devices utilizing coherent transport through molecular scale multiply-connected geometries in the presence of moderate magnetic fields is presented. It is shown how two types of simple devices, spin filters and spin splitters (or Stern-Gerlach devices) may be constructed from molecular nanometric rings utilizing the Aharonov-Bohm

S. Durr, Z. Fodor, C. Hoelbling, S. D. Katz

We present preliminary results for the chiral behavior of charged pseudo-Goldstone-boson masses and decay constants. These are obtained in simulations with N_f=2+1 flavors of tree-level, O(a)-improved Wilson sea quarks. In these simulations, mesons are composed of either valence quarks discretized in the same way as the sea quarks (unitary simulations) or of

Edward J. Wegman, Wendy L. Martinez

In 1946, Public Law 588 of the 79th Congress established the Office of Naval Research (ONR). Its mission was to plan, foster and encourage scientific research in support of Naval problems. The establishment of ONR predates the National Science Foundation and initiated the refocusing of scientific infrastructure in the United States following World War II. At

D. Bauso, L. Giarré, R. Pesenti

We consider a continuous time linear multi inventory system with unknown demands bounded within ellipsoids and controls bounded within ellipsoids or polytopes. We address the problem of "-stabilizing the inventory since this implies some reduction of the inventory costs. The main results are certain conditions under which "-stabilizability is possibl

G. M. Link, N. Vijaykrishnan

Many existing thermal management techniques focus on reducing the overall power consumption of the chip, and do not address location-specific temperature problems referred to as hotspots. We propose the use of dynamic runtime reconfiguration to shift the hotspot-inducing computation periodically and make the thermal profile more uniform. Our analysis shows t

Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed

Takeshi Kitahara, Naoyuki Kawabe, Fimihiro Minami, Katsuhiro Seta

This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.

D. C. Keezer, C. Gray, A. Majid, N. Taher

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core p

A. Verle, X. Michel, N. Azemard, P. Maurine

Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form model of delay in CMOS structures to define metrics for a deterministic selection of the optimization alternati

J. L. Rossello, V. Canals, S. A. Bota, A. Keshavarzi

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact

Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu

A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construct a fully-preemptive schedule that leads to minimum energy consumption when the tasks take on approximately the average execution cycles yet still guarantees no deadline violation d

Celia Lopez-Ongil, Mario Garcia-Valderas, Marta Portela-Garcia, Luis Entrena-Arrontes

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently required in many applications where Fault Tolerance (FT) was not a requirement in the very near past. The use of platform FPGAs for the

Kris Tiri, Ingrid Verbauwhede

Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power dissipation independent of the input signals, are used in securi

Fernando Rincon, Francisco Moya, Jesus Barba, Juan Carlos Lopez

Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices have embraced different approaches to this problem. Software designs are usually modelled after a set of proven solutions to recurrent problems called design patterns. This approach

Philippe Martin

Research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures but have not focused on compatibility communication standards. This paper describes a number of issues faced when designing a VC-neutral NoC, i.e. compatible with standards such as AHB 2.0, AXI, VCI, OCP, and various other propr

Reinhold Heckmann, Christian Ferdinand

Static program analysis by abstract interpretation is an efficient method to determine properties of embedded software. One example is value analysis, which determines the values stored in the processor registers. Its results are used as input to more advanced analyses, which ultimately yield information about the stack usage and the timing behavior of embed

Jawad Khan, Ranga Vemuri

In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main processing element. An application is modeled in the form of a precedence task graph at a coarse level of granularity. We assume that for each task in the task graph several unique design

Lars Wehmeyer, Peter Marwedel

Safety-critical embedded systems having to meet real-time constraints are expected to be highly predictable in order to guarantee at design time that certain timing deadlines will always be met. This requirement usually prevents designers from utilizing caches due to their highly dynamic, thus hardly predictable behavior. The integration of scratchpad memori

L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli

Single Event Upsets (SEU) as well as permanent faults can significantly affect the correct on-line operation of digital systems, such as memories and microprocessors; a memory can be made resilient to permanent and transient faults by using modular redundancy and coding. In this paper, different memory systems are compared: these systems utilize simplex and

Mariano Ciccolini, Ansgar Denner, Stefan Dittmaier

The radiative corrections of the strong and electroweak interactions are calculated at next-to-leading order for Higgs-boson production in the weak-boson-fusion channel at hadron colliders. Specifically, the calculation includes all weak-boson fusion and quark--antiquark annihilation diagrams to Higgs-boson production in association with two hard jets, inclu

Wolfgang Klingauf

This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both application-specific HW and SW components of an embedded system using the TLM approach, thus allowing for fast communication architecture exploration, rapid prototyping and early em

Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey

Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has heavy impact on the reliability of SOCs. Transparent test is one of useful technique for improving the reliability of memories during life time. This paper presents a systematic algorithm used for transforming

M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLDL) like SystemC. We describe these constructs and show how they are used to build a simulation model of an RTOS kernel targeting the $μ$-ITRON OS specification standard.

Joachim Langenwalter

Model based design enables the automatic generation of final-build software from models for high-volume automotive embedded systems. This paper presents a framework of processes, methods and tools for the design of automotive embedded systems. A steer-by-wire system serves as an example.

D. Volchenkov, R. Lima

A simple generalization of the MHD model accounting for the fluctuations of the configurations due to kinetic effects in plasmas in short times small scales is considered. The velocity of conductive fluid and the magnetic field are considerd as the stochastic fields (or random trial trajectories) for which the classical MHD equations play the role of the mea

Alan Mishchenko, Robert Brayton, Roland Jiang, Tiziano Villa

A class of discrete event synthesis problems can be reduced to solving language equations f . X ⊆ S, where F is the fixed component and S the specification. Sequential synthesis deals with FSMs when the automata for F and S are prefix closed, and are naturally represented by multi-level networks with latches. For this special case, we present an efficie

Joel Coburn, Srivaths Ravi, Anand Raghunathan

In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given

Jan Forbriger, Vladimir Galindo, Gunter Gerbeth, Frank Stefani

Harmonic and transient eddy currents in a liquid metal positioned above an excitation coil are determined by measuring the voltage drop in a simple potential probe. The resulting spatio-temporal eddy current field is compared with the corresponding analytical expressions for a conducting half-space. Further, a deformation of the eddy current distribution due

Horst Brinkmeyer

Carefully tested electric/electronic components are a requirement for effective hardware-in-the-loop tests and vehicle tests in automotive industry. A new method for definition and execution of component tests is described. The most important advantage of this method is independance from the test stand. It therefore offers the oppportunity to build up knowle

Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan

When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the technique on low end processor and tight-budget memory. Furthermore, it should have the capability to track time varying behavior rapidly because the time varying is an inherent char

Cesar Marcon, Ney Calazans, Fernando Moraes, Altamiro Susin

Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoCs). Modeling applications involves capturing its computation and communica

Karsten Albers, Frank Slomka

This paper presents new fast exact feasibility tests for uniprocessor real-time systems using preemptive EDF scheduling. Task sets which are accepted by previously described sufficient tests will be evaluated in nearly the same time as with the old tests by the new algorithms. Many task sets are not accepted by the earlier tests despite them beeing feasible.

L. Lopez, J. M. Portal, D. Nee

The embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The integration of the DRAM capacitor process into a logic process is challenging to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (~30F) of this device induce problems of process monitoring and failure analysis. We propose a new test stru

Irith Pomeranz, Sudhakar M. Reddy

Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform both a worst-case analysis and an average-case analysis to check the effect of restricting n on the unmodeled fault coverage of an (arbitrary) n-detection test set. Our analysis is

Eric Liau, Doris Schmitt-Landsiedel

Characterization of semiconductor devices is used to gather as much data about the device as possible to determine weaknesses in design or trends in the manufacturing process. In this paper, we propose a novel multiple trip point characterization concept to overcome the constraint of single trip point concept in device characterization phase. In addition, we

S. A. Bota, M. Rosales, J. L. Rossello, J. Segura

In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of inverters to optimize their linearity. Simulation results from a 0.18$μ$m CMOS technology show that the non-linearity error o

Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan

Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications. An important milestone in this transition has been the release of the IEEE 802.15.4 standard that specifies interoperable wireless physical and medium access control layers targeted to sensor node radios. In this paper,

Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage s

G. Hamar, L. L. Zhu, P. Csizmadia, P. Levai

Recent experimental data support the presence of quark coalescence in heavy ion collisions at RHIC energies. Hadronization of quark matter and hadron formation in heavy ion collisions can be described by the coalescence process, and measured data are reproduced successfully. On the other hand, the theoretical coalescence calculations are based on a non-relat

Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy

In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage, results in the large increase of total leakage power in a logic circuit. Leakage components interact with each other in device level (through device geometry, doping profile) and also in the circuit level

Jung-Chun Kao, Radu Marculescu

As the scale of electronic devices shrinks, "electronic textiles" (e-textiles) will make possible a wide variety of novel applications which are currently unfeasible. Due to the wearability concerns, low-power techniques are critical for e-textile applications. In this paper, we address the issue of the energy-aware routing for e-textile platforms an

Paul Muller, Armin Tajalli, Mojtaba Atarodi, Yusuf Leblebici

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simu

Carlos Eduardo Savioli, Claudio C. Czendrodi, Jose Vicente Calvano, Antonio Carneiro De Mesquita Filho

This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this concept for ATPG for diagnosing faults on analog networks. Such method relies on evolutionary techniques, where a generic algorithm (GA) is coded to generate a set of optimum freque

L. Barrandon, S. Crand, D. Houzet

The emerging concept of SoC-AMS leads to research new top-down methodologies to aid systems designers in sizing analog and mixed devices. This work applies this idea to the high-level optimization of pipeline ADC. Considering a given technology, it consists in comparing different configurations according to their imperfections and their architectures without

C. Soens, G. Van Der Plas, P. Wambacq, S. Donnay

This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resistance of the on-chip interconnect in the impact mechanism. This methodology allows investigation of the role of the separate devices (also parasitic devices) in the analog / RF circ

Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used

Pekka Syri, Juha Hakkinen, Markku Moilanen

An analogue testing standard IEEE 1149.4 is mainly targeted for low-frequency testing. The problem studied in this paper is extending the standard also for radio frequency testing. IEEE 1149.4 compatible measurement structures (ABMs) developed in this study extract the information one is measuring from the radio frequency signal and represent the result as a

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee

Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing suscept

Sounil Biswas, Peng Li, R. D., Blanton

Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing e-SVM based statistical learning. Application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that r

Marcelo Negreiros, Luigi Carro, Altamiro A. Susin

A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of noise figure in several test points of the analog circuit. The method is also able to benefit from SoC resources, like memory and processing power. Theoretical background and experi

Raoul F. Badaoui, Ranga Vemuri

This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generated only once for a specific circuit topology. When used in synthesis, these pre-generated structures instantiate various layout floorplans for various sizes and parameters of a circ

Zhi Guo, Betul Buyukkurt, Walid Najjar, Kees Vissers

FPGAs, as computing devices, offer significant speedup over microprocessors. Furthermore, their configurability offers an advantage over traditional ASICs. However, they do not yet enjoy high-level language programmability, as microprocessors do. This has become the main obstacle for their wider acceptance by application designers. ROCCC is a compiler design

Jonathan R. Carter, Sule Ozev, Daniel J. Sorin

As device sizes shrink and current densities increase, the probability of device failures due to gate oxide breakdown (OBD) also increases. To provide designs that are tolerant to such failures, we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level. In this paper, we develop a model for operational

Jia Yu, Wei Wu, Xi Chen, Harry Hsieh

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-

Osama Neiroukh, Xiaoyu Song

A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufactur

Ghazanfar Asadi, Mehdi B. Tahoori

In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Experiments results and comparison of the results with the random simulation technique show that our proposed method is on average within 6% of the random simulation method and four to f

N. Huot, H. Dubreuil, L. Fesquet, M. Renaudin

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit w

Ali Iranli, Hanif Fatemi, Massoud Pedram

In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display. This is achieved by finding a pixel transformation function, which maps the original image histogram to a new histogram with lower dynamic range. Next the contr

Georges Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, t

Gernot Krobath, representing the ATLAS/CMS collaborations

Many models of physics beyond the Standard Model are based on extended gauge symmetries and predict the existence of new heavy particles, often at the TeV scale. Such particles include heavy W and Z bosons, doubly charged higgses, heavy majorana neutrinos, leptoquarks and heavy fermions. The discovery potential of the LHC, which will start in 2008, for vario

Umit Y. Ogras, Radu Marculescu

In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an important problem, particularly for network-based implementations of complex applications. Our approach is based on using frequently encountered generic communication primitives as an al

Rui Rodrigues, Joao M. P. Cardoso

This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We beli

Roman Lysecky, Frank Vahid

Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their

Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung

Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements.