October 2007 arXiv papers — page 14

Tohru Ishihara, Farzan Fallah

This paper presents a technique for eliminating redundant cache-tag and cache-way accesses to reduce power consumption. The basic idea is to keep a small number of Most Recently Used (MRU) addresses in a Memory Address Buffer (MAB) and to omit redundant tag and way accesses when there is a MAB-hit. Since the approach keeps only tag and set-index values in th

Nastaran Baradaran, Pedro C. Diniz

The aggressive application of scalar replacement to array references substantially reduces the number of memory operations at the expense of a possibly very large number of registers. In this paper we describe a register allocation algorithm that assigns registers to scalar replaced array references along the critical paths of a computation, in many cases ex

Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee

This paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs transaction-level model of the remaining part of the whole chip being verified. With conventional simulation accelerator, evaluations of s

Greg Stitt, Frank Vahid

In this paper, we present a software compilation approach for microprocessor/FPGA platforms that partitions a software binary onto custom hardware implemented in the FPGA. Our approach imposes less restrictions on software tool flow than previous compiler approaches, allowing software designers to use any software language and compiler. Our approach uses a b

Ambar A. Gadkari, S. Ramesh

Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked Event Sequence Chart). CESC is a visual language designed for specifying system level interactions involving single and multiple c

Aseem Agarwal, Kaviraj Chopra, David Blaauw

The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for SSTA-based circuit optimization. In this paper, we propose a new sensitivity based, statistical gate sizing method. Since brute-force computation of the change in circuit delay distribution to gate size chan

Alan Mishchenko, Robert K. Brayton

This paper describes an improved approach to Boolean network optimization using internal don't-cares. The improvements concern the type of don't-cares computed, their scope, and the computation method. Instead of the traditionally used compatible observability don't-cares (CODCs), we introduce and justify the use of complete don't-cares (CDC)

Guowu Yang, William N. N. Hung, Xiaoyu Song, Marek Perkowski

We propose an approach to optimally synthesize quantum circuits from non-permutative quantum gates such as Controlled-Square-Root-of-Not (i.e. Controlled-V). Our approach reduces the synthesis problem to multiple-valued optimization and uses group theory. We devise a novel technique that transforms the quantum logic synthesis problem from a multi-valued cons

Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e.

K. -U. Kirstein, Y. Li, M. Zimmermann, C. Vancura

Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integ

Zhuo Li, Weiping Shi

Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer insertion algorithm of van Ginneken has time complexity O(n^2), where n is the number of buffer positions. Lillis, Cheng and Lin extended van Ginneken's algorithm to allow b buffer types in time O (b^2 n^2). For modern design libraries that contain hundreds of bu

Xun Liu, Yuantao Peng, Marios C. Papaefthymiou

This paper presents a novel repeater insertion algorithm for interconnect power minimization. The novelty of our approach is in the judicious integration of an analytical solver and a dynamic programming based method. Specifically, the analytical solver chooses a concise repeater library and a small set of repeater location candidates such that the dynamic p

K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens

Development of energy and performance-efficient embedded software is increasingly relying on application of complex transformations on the critical parts of the source code. Designers applying such nontrivial source code transformations are often faced with the problem of ensuring functional equivalence of the original and transformed programs. Currently the

F. Lima Kastensmidt, L. Sterpone, L. Carro, M. Sonza Reorda

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can gen

Sandeep Kumar Goel, Erik Jan Marinissen

Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to

Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty

Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to

C. Bolchini, F. Salice, D. Sciuto, L. Pomante

The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level, a

S. Tosun, N. Mansouri, E. Arvas, M. Kandemir

Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and component shut-down. As a result, it is becoming necessary to treat reliability as a first-class citiz

Stephen A. Edwards

MANY TECHNIQUES for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. This paper looks at two of the fundamental challenges: concurrency and timing control.

Ian Oliver

Traditionally system design has been made from a black box/functionality only perspective which forces the developer to concentrate on how the functionality can be decomposed and recomposed into so called components. While this technique is well established and well known it does suffer fromsome drawbacks; namely that the systems produced can often be forced

Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard

As Moore's Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completing designs. In particular, the system interconnect must efficiently service a diverse set of data flows with widely ranging quality-of-service (QoS) requirements. However, the kno

Diana Marculescu

The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical framework that is able to assess the trade-offs existing in nanoscale designs between the amount of redundancy needed for a given level of resilience to errors and the associated energy

Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor Mudge

On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating conditions. In this paper, we propose a dynamic voltage scaling (DVS) technique for buses, based on a d

R. Thewes, C. Paulus, M. Schienle, F. Hofmann

CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

Miriam Ciavarella

We fix $\ell$ a prime and let $M$ be an integer such that $\ell\not|M$; let $f\in S_2(Γ_1(M\ell^2))$ be a newform supercuspidal of fixed type related to the nebentypus, at $\ell$ and special at a finite set of primes. Let $\TT^ψ$ be the local quaternionic Hecke algebra associated to $f$. The algebra $\TT^ψ$ acts on a module $\mathcal M^ψ_f$ coming from the c

I. M. Savukov, V. A. Dzuba

Relativistic Hartree-Fock method together with many-body perturbation theory and configuration interaction techniques are used to calculate relativistic energy shifts for frequencies of the strong electric dipole transitions of C III, C IV, Na I, Mg I, Mg II, Al II, Al III, Si IV, Ca II and Zn II. These transitions are used for search of the variation of the

Tathagata Banerjee, Rahul Mukerjee

Shoutir Kishore Chatterjee was born in Ranchi, a small hill station in India, on November 6, 1934. He received his B.Sc. in statistics from the Presidency College, Calcutta, in 1954, and M.Sc. and Ph.D. degrees in statistics from the University of Calcutta in 1956 and 1962, respectively. He was appointed a lecturer in the Department of Statistics, University

Fei Su, Krishnendu Chakrabarty

Microfluidics-based biochips are soon expected to revolutionize clinical diagnosis, DNA sequencing, and other laboratory procedures involving molecular biology. Most microfluidic biochips are based on the principle of continuous fluid flow and they rely on permanently-etched microchannels, micropumps, and microvalves. We focus here on the automated design of

Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula

As microfluidics-based biochips become more complex, manufacturing yield will have significant influence on production volume and product cost. We propose an interstitial redundancy approach to enhance the yield of biochips that are based on droplet-based microfluidics. In this design method, spare cells are placed in the interstitial sites within the microf

Srinivasan Murali, Giovanni De Micheli

As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to increase, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent trend that many of the standard bus products such as STbus, have now introduced the capability of desig

Ilia Polian, Alejandro Czutro, Bernd Becker

We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In contrast to existing code-based methods, we allow unspecified values in matching vectors, which allows encoding of arbitrary test sets using a relatively small number of code-words. E

Cheng-Wen Wu

On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. The chip has been fabricated and tested successfully by our approach. Test results justify that s

Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin

We present our experience of designing a single-chip controller for advanced digital still camera from specification all the way to mass production. The process involves collaboration with camera system designer, IP vendors, EDA vendors, silicon wafer foundry, package and testing houses, and camera maker. We also co-work with academic research groups to deve

Malay K. Ganai, Aarti Gupta, Pranav Ashar

We describe verification techniques for embedded memory systems using efficient memory modeling (EMM), without explicitly modeling each memory bit. We extend our previously proposed approach of EMM in Bounded Model Checking (BMC) for a single read/write port single memory system, to more commonly occurring systems with multiple memories, having multiple read

Nicolo Manaresi, Gianni Medoro, Melanie Abonnenc, Vincent Auger

Application of Microelectronic to bioanalysis is an emerging field which holds great promise. From the standpoint of electronic and system design, biochips imply a radical change of perspective, since new, completely different constraints emerge while other usual constraints can be relaxed. While electronic parts of the system can rely on the usual establish

Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee

Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to es

Olav Geil, Ryutaroh Matsumoto

Let Lambda be a numerical semigroup. Assume there exists an algebraic function field over GF(q) in one variable which possesses a rational place that has Lambda as its Weierstrass semigroup. We ask the question as to how many rational places such a function field can possibly have and we derive an upper bound in terms of the generators of Lambda and q. Our b

C. Chiang, A. Kahng, S. Sinha, X. Xu

As feature sizes shrink, it will be necessary to use AAPSM (Alternating-Aperture Phase Shift Masking) to image critical features, especially on the polysilicon layer. This imposes additional constraints on the layouts beyond traditional design rules. Of particular note is the requirement that all critical features be flanked by opposite-phase shifters, while

W. -L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir

Temperature affects not only the reliability but also the performance, power, and cost of the embedded system. This paper proposes a thermal-aware task allocation and scheduling algorithm for embedded systems. The algorithm is used as a sub-routine for hardware/software co-synthesis to reduce the peak temperature and achieve a thermally even distribution whi

Pierre Bomel, Eric Martin, Emmanuel Boutillon

In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach

A. M. Molnos, M. J. M. Heijligers, S. D. Cotofana, J. T. J. Van Eijndhoven

Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is difficult to predict and the integration of new tasks expensive. This paper proposes a new method that imposes compositi

Gh. Bodean, D. Bodean, A. Labunetz

This paper gives an overview of a new technique, named pseudo-ring testing (PRT). PRT can be applied for testing wide type of random access memories (RAM): bit- or word-oriented and single- or dual-port RAM's. An essential particularity of the proposed methodology is the emulation of a linear automaton over Galois field by memory own components.

Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor

The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-layered memory hierarchies as a means to design energy and performance efficient systems. However, most of the previous work do not explore trade-offs systematically. We fill this ga

Baosheng Wang, Yuejian Wu, Andre Ivanov

This paper proposes a diagnosis scheme aimed at reducing diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves the one proposed in [A parallel built-in self-diagnostic method for embedded memory buffers, A parallel built-in self-diagnostic method for embedded memory arrays]. The improvements are mainly two-fold. On one hand, the

Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi

Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model orde

Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha

Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in future technologies the static portion of power dissipation will outreach the dynamic portion. This paper proposes an efficient technique to reduce both dynamic and static power dissipa

Mahmut Kandemir, Guilin Chen

Utilizing on-chip caches in embedded multiprocessor-system-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work that targets at optimizing cache behavior are performed at hardware and compilation levels, operating system (OS) can also play major role as it sees the global access pattern inform

C. Zhao, W. -T. Ni, E. Samain

To advance from milli-arcsecond to micro-arcsecond astrometry, time keeping capability and its comparison among different stations need to be improved and enhanced. The T2L2 (Time transfer by laser link) experiment under development at OCA and CNES to be launched in 2008 on Jason-2, allows the synchronization of remote clocks on Earth. It is based on the pro

Praveen Ghanta, Sarma Vrudhula, Rajendran Panda, Janet Wang

In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid's electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an

Olli Martio, Vladimir M. Miklyukov, Matti Vuorinen

Some counterparts of theorems of Phragmén-Lindelöf and of Ahlfors are proved for differential forms of ${\cal WT}$--classes.}

Carlos E. Román-Velázquez, Bo E. Sernelius

We use multipolar expansions to find the force on a gold coated sphere above a gold substrate; we study both an empty gold shell and a gold coated polystyrene sphere. We find four characteristic separation ranges. In the first region, which for the empty gold shell occurs for distances, d, smaller than the thickness of the coating, the result agrees with tha

O. Villa, P. Schaumont, I. Verbauwhede, M. Monchiero

In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine's memory management capabilities, dynamic data processing is supported without compromising speed and accuracy of the simulation. A first prototype in a shared memory context is presented.

B. Cheon, E. Lee, L. -T. Wang, X. Wen

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely use

Jurgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel

In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel to the execution of the

Mehrdad Reshadi, Nikil Dutt

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In thi

Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin

A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Conventional STA tools represent a waveform by its arrival time and slope. However, this is not an accurate way of modeling the waveform for th

Tim Schattkowsky

The design productivity gap requires more efficient design methods. Software systems have faced the same challenge and seem to have mastered it with the introduction of more abstract design methods. The UML has become the standard for software systems modeling and thus the foundation of new design methods. Although the UML is defined as a general purpose mod

Ilya Issenin, Nikil Dutt

In today's embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the use of scratch pad memories, with many based on static analysis of a program. However, often it is not possible to perform static analysis and optimization of a program's memor

Cristiano Forzan, Davide Pandini

In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling capacitances, must be considered in order to accurately estimate the overall noise impact on design functionality and performances. In this work the impact of the cell non-linearity

Sankalp S. Kallakuri, Alex Doboli, Eugene A. Feinberg

We have presented an optimal buffer sizing and buffer insertion methodology which uses stochastic models of the architecture and Continuous Time Markov Decision Processes CTMDPs. Such a methodology is useful in managing the scarce buffer resources available on chip as compared to network based data communication which can have large buffer space. The modelin

Irith Pomeranz, Sudhakar M. Reddy

We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI (f) with every circuit fault f. The heuristic estimates the number of faults that will be detected by a test generated for f. Fault ordering is done such that a fault with a higher

Stephen J. Mellor, John R. Wolfe, Campbell Mccausland

Let's be clear from the outset: SoC can most certainly make use of UML; SoC just doesn't need more UML, or even all of it. The advent of model mappings, coupled with marks that indicate which mapping rule to apply, enable a major simplification of the use of UML in SoC.

Tadashi Takeuchi

Demands for implementing original OSs that can achieve high I/O performance on PC/AT compatible hardware have recently been increasing, but conventional OS debugging environments have not been able to simultaneously assure their stability, be easily customized to new OSs and new I/O devices, and assure efficient execution of I/O operations. We therefore deve

Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Wang

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay analy

Bharat Sukhwani, Uday Padmanabhan, Janet M. Wang

New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's scaling limitations. However, many such devices exhibit non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach tha

Nikolaos Kavvadias, Spiridon Nikolaidis

In this paper, the program control unit of an embedded RISC processor is enhanced with a novel zero-overhead loop controller (ZOLC) supporting arbitrary loop structures with multiple-entry/exit nodes. The ZOLC has been incorporated to an open RISC processor core to evaluate the performance of the proposed unit for alternative configurations of the selected p

Trent Mcconaghy, Tom Eeckelaert, Georges Gielen

This paper presents a method to automatically generate compact symbolic performance models of analog circuits with no prior specification of an equation template. The approach takes SPICE simulation data as input, which enables modeling of any nonlinear circuits and circuit characteristics. Genetic programming is applied as a means of traversing the space of

Jacob Katz, Ziyad Hanna, Nachum Dershowitz

Current algorithms for bounded model checking use SAT methods for checking satisfiability of Boolean formulae. These methods suffer from the potential memory explosion problem. Methods based on the validity of Quantified Boolean Formulae (QBF) allow an exponentially more succinct representation of formulae to be checked, because no "unrolling" of the

V. A. Gasparov, I. Sheikin, F. Levy, J. Teyssier

The de Haas - van Alphen (dHvA) effect in the cluster superconductor ZrB12 was studied by magnetic torque measurements in magnetic fields up to 28 T at temperatures down to 0.35 K. The dHvA oscillations due to orbits from the Neck sections and "Cubic Box" of the Fermi surface were detected. We measured cyclotron effective masses of 0.5m_0 for Neck se

Xiu-San Xing

Why can the world resist the law of entropy increase and produce self-organizing structure? Does the entropy of an isolated system always only increase and never decrease? Can be thermodymamic degradation and self-organizing evolution united? How to unite? In this paper starting out from nonequilibrium entropy evolution equation we proved that a new entropy

J. Kildea, J. Zweerink, J. Ball, J. E. Carson

We present the analysis and results of 12.5 hours of high-energy gamma-ray observations of the EGRET-detected pulsar PSR B1951+32 using the Solar Tower Atmospheric Cherenkov Effect Experiment (STACEE). STACEE is an atmospheric Cherenkov detector, in Albuquerque, New Mexico, that detects cosmic gamma rays using the shower-front-sampling technique. STACEE'

Sharon-Lise T. Normand, David M. Shahian

Hospital profiling involves a comparison of a health care provider's structure, processes of care, or outcomes to a standard, often in the form of a report card. Given the ubiquity of report cards and similar consumer ratings in contemporary American culture, it is notable that these are a relatively recent phenomenon in health care. Prior to the 1986 re

C. Alexandrou, G. Koutsou, H. Neff, J. W. Negele

The electromagnetic nucleon to Delta transition form factors are evaluated using two degenerate flavors of dynamical Wilson fermions and using dynamical sea staggered fermions with domain wall valence quarks. The two subdominant quadrupole form factors are evaluated for the first time in full QCD to sufficient accuracy to exclude a zero value, which is taken

Zheng Ze Ma

From the constructions of the quantum spacetime, a four dimensional quantized spacetime can be embedded in a five dimensional continuous spacetime. Thus to observe from the five dimensional continuous spacetime where the four dimensional quantized spacetime is embedded, there exist the energy-momentum flows between the five dimensional continuous spacetime a

Feng Liang, Sayan Mukherjee, Mike West

The incorporation of unlabeled data in regression and classification analysis is an increasing focus of the applied statistics and machine learning literatures, with a number of recent examples demonstrating the potential for unlabeled data to contribute to improved predictive accuracy. The statistical basis for this semisupervised analysis does not appear t

Dragi Anevski, Anne-Laure Fougères

The monotone rearrrangement algorithm was introduced by Hardy, Littlewood and Pólya as a sorting device for functions. Assuming that $x$ is a monotone function and that an estimate $x_n$ of $x$ is given, consider the monotone rearrangement $\hat{x}_n$ of $x_n$. This new estimator is shown to be uniformly consistent. Under suitable assumptions, pointwise limi

N. Rey, P. Toulemonde, D. Machon, L. Duclaux

The high pressure phase diagram of CsC8 graphite intercalated compound has been investigated at ambient temperature up to 32 GPa. Combining X-ray and neutron diffraction, Raman and X- ray absorption spectroscopies, we report for the first time that CsC8, when pressurized, undergoes phase transitions around 2.0, 4.8 and 8 GPa. Possible candidate lattice struc

J. H. Sepanski, Lingji Kong

The mathematical properties of a family of generalized beta distribution, including beta-normal, skewed-t, log-F, beta-exponential, beta-Weibull distributions have recently been studied in several publications. This paper applies these distributions to the modeling of the size distribution of income and computes the maximum likelihood estimation estimates of

Anurag Shrinagar, Ashish Garg, Rajendra Prasad

Experimental data on the structure of ferroelectric oxide Bismuth Titanate suggests two different kinds of structures i.e. orthorhombic and monoclinic. We have performed density functional theory (DFT) based first principle calculations to determine the ground state structure of bismuth titanate, based on experimentally observed monoclinic and orthorhombic p

Dmitrii N. Maksimov, Almas F. Sadreev

Similar to the Berry conjecture of quantum chaos we consider elastic analogue which incorporates longitudinal and transverse elastic displacements with corresponding wave vectors. Based on that we derive the correlation functions for amplitudes and intensities of elastic displacements. Comparison to numerics in a quarter Bunimovich stadium demonstrates excel

Emiko Arahata, Tetsuro Nikuni

We study damping of a dipole oscillation in a Bose-Condensed gas in a combined cigar-shaped harmonic trap and one-dimensional (1D) optical lattice potential at finite temperatures. In order to include the effect of thermal excitations in the radial direction, we derive a quasi-1D model of the Gross-Pitaeavskii equation and the Bogoliubov equations. We use th

W. R. G. James, I. Jensen, A. J. Guttmann

Polygons are described as almost-convex if their perimeter differs from the perimeter of their minimum bounding rectangle by twice their `concavity index', $m$. Such polygons are called \emph{$m$-convex} polygons and are characterised by having up to $m$ indentations in the side. We use a `divide and conquer' approach, factorising 2-convex polygons b

Joshua D. Batson

Let $p$ be a prime, and let $\mathbb{Z}_p$ denote the field of integers modulo $p$. The \emph{Nathanson height} of a point $v \in \mathbb{Z}_p^n$ is the sum of the least nonnegative integer representatives of its coordinates. The Nathanson height of a subspace $V \subseteq \mathbb{Z}_p^n$ is the least Nathanson height of any of its nonzero points. In this pa

Takeshi Higashi, Kiyoshi Higashijima, Etsuko Itou

We construct supersymmetric conformal sigma models in three dimensions. Nonlinear sigma models in three dimensions are nonrenormalizable in perturbation theory. We use the Wilsonian renormalization group equation method, which is one of the nonperturbative methods, to find the fixed points. Existence of fixed points is extremely important in this approach to

Alastair Hamilton

In this paper we show that the homology of a certain natural compactification of the moduli space, introduced by Kontsevich in his study of Witten's conjectures, can be described completely algebraically as the homology of a certain differential graded Lie algebra. This two-parameter family is constructed by using a Lie cobracket on the space of noncommu

D. L. Band, J. E. Grindlay, J. Hong, G. Fishman

We use semi-analytic techniques to evaluate the burst sensitivity of designs for the EXIST hard X-ray survey mission. Applying these techniques to the mission design proposed for the Beyond Einstein program, we find that with its very large field-of-view and faint gamma-ray burst detection threshold, EXIST will detect and localize approximately two bursts pe

Xuefei Chen, Zhanwen Han

We constructed some main-sequence mergers from case A binary evolution and studied their characteristics via Eggleton's stellar evolution code. Both total mass and orbital angular momentum are conservative in our binary evolutions. Some mergers might be on the left of the ZAMS as defined by normal surface composition on a CMD because of enhanced surface

Yoshiyuki Morisawa, Shinya Tomizawa, Yukinori Yasui

We study the boundary value problem for asymptotically flat stationary black ring solutions to the five-dimensional vacuum Einstein equations. Assuming the existence of two additional commuting axial Killing vector fields and the horizon topology of $S^1\times S^2$, we show that the only asymptotically flat black ring solution with a regular horizon is the P

Claudia de Rham

The curvature on codimension-two and higher branes is not regular for arbitrary matter sources. Nevertheless, the low-energy theory for an observer on such a brane should be well-defined and independent to any regularization procedure. This is achieved via appropriate classical renormalization of the brane couplings, and leads to a natural hierarchy between

Naoto Morikawa

Local protein structure analysis is informative to protein structure analysis and has been used successfully in protein structure prediction and others. Proteins have recurring structural features, such as helix caps and beta turns, which often have strong amino acid sequence preferences. And the challenges for local structure analysis have been identificati

Siyuranga O. Koswatta, Mark S. Lundstrom, Dmitri E. Nikonov

Power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this letter, we study p-i-n band-to-band tunneling field effect transistors (TFET) taking semiconducting carbon nanotubes as the channel material. The on-current of these devices is ma

L. C. Garcia de Andrade

A solution of magnetic Hall equations for plasma filaments in the Coulomb gauge is obtained in the non-holonomic frame. Some physical features of the solution include, the non-conservation of the magnetic helicity and the decay of the magnetic field in the filaments. From the mathematical point of view,the presence of Frenet torsion in the filament is actual

Spencer Chang, Neal Weiner

Experimental and theoretical clues both suggest that the Higgs boson has a mass below the LEP2 lower limit of 114.4 GeV. If true, this suggests that the dominant Higgs decay is nonstandard while the production cross sections remain unmodified. We consider the possibility of nonstandard Higgs decays in the language of On-Shell Effective Theories (OSETs), and

Alfio Bonanno, Vadim Urpin

Stability properties of magnetic-field configurations containing the toroidal and axial field are considered. The stability is treated by making use of linear analysis. It is shown that the conditions required for the onset of instability are essentially different from those given by the necessary condition $d (s B_ϕ)/ds > 0$, where $s$ is the cylindrical ra

Rebecca A. Metzler, Dong Zhou, Mike Abrecht, Susan N. Coppersmith

Red abalone nacre is an intensely studied biomineral, and yet its formation mechanism remains poorly understood. Here we report quantitative measurements probing the degree of order of the aragonite tablets in nacre, and show that order develops over a distance of about 50 microns. These observations indicate that the orientational order of aragonite tablets

N. A. Hatch, R. A. Overzier, H. J. A. Röttgering, J. D. Kurk

We present detailed images of diffuse UV intergalactic light (IGL), situated in a 60kpc halo that surrounds the radio galaxy MRC 1138-262 at z=2. We discuss the nature of the IGL and rule out faint cluster galaxies, nebular continuum emission, synchrotron, inverse Compton emission and scattering of galactic stellar light as possible sources of the IGL. Dust

Eric C. Bellm, Kevin Hurley, Valentin Pal'shin, Kazutaka Yamaoka

The long, bright gamma-ray burst GRB 070125 was localized by the Interplanetary Network. We present light curves of the prompt gamma-ray emission as observed by Konus-WIND, RHESSI, Suzaku-WAM, and \textit{Swift}-BAT. We detail the results of joint spectral fits with Konus and RHESSI data. The burst shows moderate hard-to-soft evolution in its multi-peaked em

Yu Zhang

We independently assign a non-negative value, as a capacity for the quantity of flows per unit time, with a distribution F to each edge on the Z^d lattice. We consider the maximum flows through the edges of two disjoint sets, that is from a source to a sink, in a large cube. In this paper, we show that the ratio of the maximum flow and the size of source is

Oana Chis, Mircea Puta

The paper presents some dynamical aspects of Rabinovich type, with distributed delay and with fractional derivatives.

Ying Ran, Wing-Ho Ko, Patrick A. Lee, Xiao-Gang Wen

The Dirac spin liquid was proposed to be the ground state of the spin-1/2 Kagome antiferromagnets. In a magnetic field $B$, we show that the state with Fermi pocket is unstable to the Landau level (LL) state. The LL state breaks the spin rotation around the axis of the magnetic field. We find that the LL state has an in-plane 120$^{\circ}$ $q=0$ magnetizatio