A Comprehensive Study of Charge-Carrier Mobility in Double Lateral-Gate Silicon Junctionless Transistors

Abstract

We give in depth overview of charge-carrier mobility in p-type silicon double lateral-gate junctionless transistors (DLGJLT) through a mix of computer simulations and experimental results. The devices were built on low-doped silicon-on-insulator substrates using atomic force microscope nanolithography. Because the design uses air-gap side gates instead of a gate-oxide layer or junction, it allows electrical current to flow through a lightly doped silicon channel. This setup reduces impurity scattering and protects transport quality from interface damage. We used three-dimensional TCAD Sentaurus simulation tool to model the device's electrical behavior and confirm our experimental data for transconductance and drain conductance. We attempt to give a comprehensive view on the charge transition within the device.