FPGA Co-processor for the ALICE High Level Trigger
G. Grastveit, H. Helstrup, V. Lindenstruth, C. Loizides, D. Roehrich, B. Skaali, T. Steinbeck, R. Stock, H. Tilsner, K. Ullaland, A. Vestbo, T. Vik
Abstract
The High Level Trigger (HLT) of the ALICE experiment requires massive parallel computing. One of the main tasks of the HLT system is two-dimensional cluster finding on raw data of the Time Projection Chamber (TPC), which is the main data source of ALICE. To reduce the number of computing nodes needed in the HLT farm, FPGAs, which are an intrinsic part of the system, will be utilized for this task. VHDL code implementing the Fast Cluster Finder algorithm, has been written, a testbed for functional verification of the code has been developed, and the code has been synthesized
Create a lesson
Related papers
Hydrogen Electron Cyclotron Resonance Dissociator Demonstrator for the Project 8 Experiment
Manjinder Oueslati, Walter Pettus, Anna Reine et al.
On the Electrodynamics of a Non-Contact Inductive Sensor for High-Accuracy Tip Deflection Measurements of Piezoceramic Bending Actuators and its Application for Energy Harvesting Purposes
Ruediger G. Ballas
Fast Self-Triggering and Segment-Fitting of Cosmic Muons with a small-Diameter Monitored Drift Tube Detector
Shuzhe Li, Yuxiang Guo, Jiajin Ge et al.
A combined segmented anode gas ionization chamber and time-of-flight detector for heavy ion elastic recoil detection analysis
Petter Ström, Per Petersson, Marek Rubel et al.
Track reconstruction with ACTAR TPC: a transfer-reaction use case
M. Lozano-González, J. Lois-Fuentes, T. Roger et al.
Cryogenic performance of Silicon Photo-Multipliers at LN2 temperature and at 3 K in the RES-NOVA cryostat
Riccardo Rossini, Massimo Rossella, Massimiliano Clemenza et al.