The Research and Development of New Electronics System and its Testing on the JNE-1ton Prototype Detector

Abstract

The Jinping Neutrino Experiment (JNE), a next-generation neutrino observatory under construction at the China Jinping Underground Laboratory II (CJPL-II), requires high-precision waveform-based event reconstruction, imposing stringent demands on its readout electronics. To meet these requirements, we have developed a high-performance readout system featuring 1 GSa/s real-time sampling, 14-bit physical resolution with an effective number of bits (ENOB) of 10.6, a total data throughput of 64 Gbps, and a deterministic zero-delay clock distribution architecture. The new single-crate 64-channel system (PDS1500) was validated through bench tests and deployment on the upgraded JNE-1ton prototype detector. Its performance was further evaluated against a commercial reference system. The results demonstrate that all key metrics meet the JNE experimental requirements: zero data loss within a 1000 ns acquisition window, baseline noise reduced to one-third of the reference level, timing drift limited to 0.3 ns across power cycles, and an energy threshold as low as 0.1 MeV, enabling the detection of low-energy solar neutrinos. While the 14-bit physical resolution provides significantly higher waveform fidelity, the overall energy resolution in this test remains dominated by the intrinsic limitations of the JNE-1ton detector, as expected. Furthermore, the modular architecture provides the throughput and scalability required to support the full-scale 3000-channel JNE detector. These results collectively demonstrate that the newly developed electronics system fully satisfies the technical requirements of the future JNE experiment.